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| www.fairchildsemi.com AN-6208 Secondary-Side Synchronous Rectifier (SR) for LLC Resonant Converter Using FAN6208 Introduction The LLC resonant converter has drawn a lot of attention recently due to its advantages over a conventional series resonant converter and parallel resonant converter: narrow frequency variation over wide load, input variation, and Zero Voltage Switching (ZVS) for the entire load range. In an LLC resonant converter, rectifier diodes are typically used to obtain DC output voltage from the transformer secondary winding. The conduction loss of diode rectifier contributes significantly to the overall power losses in an LLC resonant converter; especially in low output voltage applications. The conduction loss of a rectifier is proportional to the product of its forward-voltage drop and the forward conduction current. Using synchronous rectification (SR) where the rectifier diode is replaced by MOSFET with a small on resistance (RDSON), the forwardvoltage drop of a synchronous rectifier can be lower than that of a diode rectifier and, consequently, the rectifier conduction loss can be reduced. FAN6208 is a synchronous rectification controller for isolated LLC or LC resonant converters that can drive two individual SR MOSFETs emulating the behavior of rectifier diodes. FAN6208 measures the SR conduction time of each switching cycle by monitoring the drain-to-source voltage of each SR and determines the optimal timing of SR gate drive. FAN6208 also uses the change of opto-coupler diode current to adaptively shrink the duration of SR gate drive signals during load transients to prevent shoot-through. To improve light-load efficiency, Green Mode disables the SR drive signals, minimizing gate drive power consumption at light-load conditions. This application note describes the design procedure for a SR circuit using FAN6208. The guidelines for printed circuit board (PCB) layout and a design example with experiment results are also presented. Figure 1 shows the typical application circuit of FAN6208. Figure 1. Typical Application (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com AN-6208 APPLICATION NOTE LLC Resonance Converter with SR Figure 2 shows the simplified schematic of a half-bridge LLC resonant converter, where Lm is the magnetizing inductance that acts as a shunt inductor, Lr is the series resonant inductor, and Cr is the resonant capacitor. Since the magnetizing inductor is relatively small, a considerable amount of magnetizing current (Im) exists, which freewheels in the primary side without being involved in the power transfer. The primary-side current (Ip) is sum of the magnetizing current and the secondary-side current referred to the primary. Figure 3 shows the typical gain curve of the half-bridge LLC resonant converter. To allow Zero Voltage Switching (ZVS) for the primary-side switches, gain curves with inductive impedance characteristics should be used, where the gain decreases as frequency increases. The resonant network has a resonant frequency determined by the resonance between Lr and Cr. When the switching frequency is lower than the resonant frequency (below resonance), the half resonance of reflected secondary-side current (diode current) finishes before the primary-side switch is turned off, as shown in Figure 4. When the switching frequency is higher than the resonant frequency (above resonance) the primary-side switch is turned off before the half resonance of reflected secondary-side current (diode current) is completed, as shown in Figure 5. Q1 Gate Q2 Gate IP Im ID ISR1 ISR2 VSR2 2*Vo SR On-time SR1 Gate Figure 4. Key Waveforms Below -Resonance Operation Figure 2. Schematic of LLC Resonant Converter with SR fo = 1 2 Lr Cr Gain ( 2nVO / VIN ) Figure 5. Key Waveforms of Above-Resonance Operation Q= Lr / Cr Rac Figure 3. Typical Gain Curves of LLC Resonant Converter (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 2 AN-6208 APPLICATION NOTE Application Circuit Figure 6 shows the typical application circuit of FAN6208 and Figure 7 shows the typical timing diagram of SR gate drive signal. FAN6208 senses the drain-to-source voltage of each SR to determine the gate drive timing. Once the body diode of SR begins conducting, the drain-to-source voltage drops to zero, which causes low detection (DETL) pin voltage to drop to zero. FAN6208 turns on the MOSFET after tON-ON-DETL (about 350ns), when the voltage on DETL drops below 2V. As depicted in Figure 8, the turn -on delay (after tSR-ON-DETL) is a sum of debounce time (150ns) and propagation delay (200ns). FAN6208 measures the SR conduction duration (tDETL), during which DETL voltage stays lower than 2V, and uses this information to determine the turn-off instant of SR gates of the next switching cycle, as shown in Figure 7. The turn-off instant is obtained by subtracting a dead time (tDEAD) from the measured SR conduction duration of the previous switching cycle. tSR-ON-DETL DETL1 2V 350ns VDETL1 tDB tPD GATE1 150ns 200ns tSR-ON-DETL DETL1 2V VDETL1 tDB GATE1 150ns 200ns tSR-ON-DETL DETL1 350ns VDETL1 2V tDB GATE1 tPD tPD 350ns 150ns 200ns Figure 8. Timing Diagram for Turning On SR Figure 6. Application Circuit of FAN6208 DETL Pin Configuration Allowable voltage on the DETL pin is from -0.3V to 7V. Since the maximum voltage of the SR drain-to-source voltage is twice that of the output voltage, a diode (DDETL) is required for the DETL pin to prevent high voltage. Diode 1N4148 is typically used for DDETL. Since the DETL internal current source is 50 A, RDETL should be determined such that the DETL voltage is lower than the low detection threshold (2V) with enough margin when the SR conducts. Since the forward-voltage drop of SR can be as low as zero when SR current is small, the DETL resistor should be: RDETL < Figure 7. SR Conduction Time Determination (2 - VFD ) 50 A (1) where VFD is the forward-voltage drop of DETL diode. RDETL larger than 20k is not typically recommended for proper low-voltage detection on DETL pin. RDETL should be determined such that the DETL voltage is higher than -0.3V when the maximum voltage drop occurs across SR, such as: (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 3 AN-6208 APPLICATION NOTE RDETL > I SR max RDS .ON - VFD - 0.3 50 A (2) where ISRmax is the maximum current of SR and RDS.ON is the maximum on-resistance of the SR MOSFET at high temperature. The RP pin has an internal constant current source (41.5 A) and the pin voltage is determined by the Rp resistor. Depending on the RP pin voltage, the Green Mode threshold of tDETL is determined as shown in Figure 12. When RRP is less than 36K , FAN6208 operates in Low-Frequency Mode, where Green Mode is enabled when tDETL is smaller than 3.75 s. When RRP is larger than 36K , HighFrequency Mode is selected and Green Mode is enabled for tDETL smaller than 1.90 s. The RP pin also has two internal thresholds for pin-open / short protection. Using RP pin short protection, remote on / off control can be implemented as shown in Figure 13. Figure 9. Application Circuit of DETL Pin RP Pin Configuration The dead time can be programmed using a resistor on the RP pin. The relationship between the dead time and SR conduction duration (tDETL) for different resistor values on the RP pin are given in Figure 10 and Figure 11. Since the SR conduction time is shrunk by the protection function (gate-shrink function) when tDEAD is smaller than 125ns, Rp should be properly selected such that the gate-shrink function does not operate at maximum switching frequency. Figure 12. RP Pin Operation Original PSON Circuit VDDSB Disable RP Pin Circuit 5VB RD RP 41.5 A VDDM RG QPSON QRP RP Figure 10. tDEAD vs. tDETL for Different RP (Low Frequency) PSON RGS 5VB Figure 13. Application Circuit of RP Pin for Remote ON / OFF Gate-Shrink Functions In normal operation, the turn-off instant is determined by subtracting a dead time (tDEAD) from the measured SR conduction duration of the previous switching cycle, as shown in Figure 7. This allows proper driving timing for the SR MOSFETS when the converter is in steady state and the switching frequency does not change much. However, this control method may cause shoot-through of SR MOSFETs when the switching frequency increases fast and switching www.fairchildsemi.com 4 Figure 11. tDEAD vs. tDETL for Different RP (High Frequency) (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 AN-6208 APPLICATION NOTE transition of the primary-side MOSFETs takes place before the turn-off command of the SR is given. To prevent the shoot-through problem, FAN6208 has gate-shrink functions. Gate shrink takes place in the following three conditions: 1. Figure 15. Application Circuit of FD Pin When an insufficient dead time is detected in the previous switching cycle. When the DETL becomes HIGH within 125ns of the detection window after SR gate is turned off, the SR gate drive signal in the next switching cycle is reduced by tSHRINK-DT (about 1.25 s) to increase the dead time as shown in Figure 14. Figure 16. Gate Shrink by Feedback Detection 3. Figure 14. Gate Shrink by Insufficient Dead Time 2. When the feedback information changes fast. FAN6208 monitors the current through the opto-coupler diode by measuring the voltage across the resistor in series with opto-diode, as depicted in Figure 15. If the feedback current through the opto diode increases by more than 20% of the feedback current of the previous switching cycle, SR gate signal is shrunk by tSHRINK-FD (about 1.4 s) for tD-SHRINK-FD (about 90 s), shown in Figure 16. When the DETL voltage has ringing around zero. As depicted in Figure 17, the drain voltage of SR has ringing around zero at light-load condition after the switching transition of primary-side switches. When DETL voltage rises above 2V within 350ns after DETL voltage drops to zero and stays above 2V longer than 150ns, the gate is shrunk by 1.2 s (tSHRINK-RNG), as shown in Figure 17. Figure 17. Gate Shrink by the DETL Voltage Ringing (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 5 AN-6208 APPLICATION NOTE Printed Circuit Board Layout In Figure 18, the power traces are marked as bold lines. Good PCB layout improves power system efficiency and reliability and minimizes EMI. As indicated by 4, the ground of the feedback loop should be connected to the negative terminal of output capacitor CO. Trace 5 should be long and far from Vo terminal. Keep trace 6 as short as possible. As indicated by 7, the source terminals of Q1 and Q2 are connected to the negative terminal of Co. Keep trace 10 short, direct, and wide. As indicated by 8, the negative terminal of Co should be connected to the case directly. Guidelines For feedback detection, the FD pin should be connected to the anode of the opto diode. Connecting the FD pin through a resistor can improve surge immunity of the system. Keep trace 1 away from any power trace with high pulsating current. The control ground (trace 2) and power ground (trace 7) should meet at a single point to minimize interference. The connecting trace should be as short as possible. Figure 18. Layout Considerations (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 6 AN-6208 APPLICATION NOTE Design Example The following example is a 12V/300W single output power supply with LLC resonant converter topology. As Figure 19 shows, the FAN7621 controller is used for the LLC resonant converter. The integrated CCM PFC controller FAN6982 is used for PFC stage. The key system parameters are listed in Table 1 and the Bill of Materials (BOM) is summarized in Table 2. The two-level PFC output voltage function of FAN6982 is used where the typical PFC output voltage is 390V. The PFC output voltage is reduced to 360V for low-line and light-load condition to improve efficiency of the PFC stage. The typical switching frequency (fs) is 65kHz for PFC stage. Table 1. System Specification 90~264VAC 360~390VDC FAN6982 FAN7621 12V 300W 65kHz 60~140kHz Input Voltage Range PFC Output PFC Controller Main power Controller Output Voltage (Vo) Output Power (Po) PFC Switching Frequency LLC resonant converter Switching Frequency The turn ratio n of TX1 is 13.5, Lm is 1.2mH, Lr is 150 H, and Cr is 47nH. 1N4148 is used for D201 & D202 whose voltage rating is 100V. 27k is used for R204 (RRP) for the Low-Frequency Mode setting. Figure 19. Complete Circuit Diagram (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 7 AN-6208 APPLICATION NOTE Table 2. Part R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 C101 C102 C103 C104 C105 C106 C107 Bill of Materials Value Resistor 10 3.3 3.3 10k 10k 1k 0.2 5.1k 9.1k 5.6k 10k 10k 10k 27k 10k 10k 10k 1k 91k 1k 33k 24k 1/4W 1/4W 1/8W 1/8W 1/8W 1/8W 2W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W Q1 Q2 Q3 450V 50V 1kV 1kV 50V 50V 50V U1 U2 U3 U4 Q4 L101 L201 D101 D102 D103 D201 D202 TX1 C108 C201 C202 C203 C204 C205 C206 C301 Note Part Value Capacitor 10F 3300F 3300F 47nF 47nF 470nF 100nF 22nF/250V Note 25V 16V 16V 50V 50V 25V 50V Y-Capacitor Transformer Lr =10H/ Lm =1200H PQ3230 Diode UF1007 1N4148 1N4148 1N4148 1N4148 1A/1000V Inductor L = 150H L = 1.8H QP2914 MOSFET FCPF11N60F FCPF11N60F FDP025N06 FDP025N06 Capacitor 270F 0.33F 150nF 47nF 12nF 100pF 680pF IC FAN7621 PC817 FAN6208 TL431 SR Controller LLC Controller (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 8 AN-6208 APPLICATION NOTE Figure 20 and Figure 21 show the SR gate drive waveforms for different RP. As can be seen, the dead time of SR drive can be programmed. The efficiency test results of the Schottky diode and synchronous rectification are shown in Table 3 and Table 4. Figure 22 compares the efficiencies of Schottky diode and synchronous rectification. As can be seen, 1~2% efficiency improvement can be obtained using synchronous rectification. Figure 22 also shows how the dead time of SR affects the efficiency. By fine-tuning the dead time, efficiency can be maximized. Table 3. Efficiency Measurements at VAC=115V on 300W PC Power with Schottky Diodes (MBRP3045) Load 100% 50% 20% Input Watts(W) 358.070 176.38 73.30 Output Watts(W) 307.658 154.91 62.19 Efficiency 85.920% 87.82% 84.80% Table 4. Efficiency Measurements at VAC=115V on 300W PC Power with SRs (FDP025N06 and RRP=30k) Load Figure 20. Secondary Side Current and SR Gate Signal by RRP=24k 100% 50% 20% Input Watts (W) 347.70 172.81 72.41 Output Watts (W) 307.62 154.77 62.21 Efficiency 88.47% 89.56% 85.91% vs. Schottky Diode +2.55% +1.74% +1.11% Figure 22. Efficiency Analysis Figure 21. Secondary Side Current and SR Gate Signal by RRP=27k (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 9 AN-6208 APPLICATION NOTE Related Resources FAN6208 -- Secondary Synchronous Rectifier Controller for LLC Topology FAN7621 -- PFM Controller for Half-Bridge Resonant Converters FAN6982 -- CCM Power Factor Correction Controller FDP025N06 --FDP025N06 N-Channel PowerTrench(R) MOSFET 60V,265A, 2.5m 1N/FDLL 914/A/B / 916/A/B / 4148 / 4448 -- Small Signal Diode FSFR2100 -- Fairchild Power Switch for Half-Bridge Resonant Converters AN4137 -- Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS) AN-4151 -- Half-Bridge LLC Resonant Converter Design Using FSFR-Series Fairchild Power Switch (FPS) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. (c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 * 3/10/11 www.fairchildsemi.com 10 |
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